`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/10/20 10:23:48
// Design Name: 
// Module Name: top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module top(
    inout   [14:0]      DDR_addr,
    inout   [2:0]       DDR_ba,
    inout               DDR_cas_n,
    inout               DDR_ck_n,
    inout               DDR_ck_p,
    inout               DDR_cke,
    inout               DDR_cs_n,
    inout   [3:0]       DDR_dm,
    inout   [31:0]      DDR_dq,
    inout   [3:0]       DDR_dqs_n,
    inout   [3:0]       DDR_dqs_p,
    inout               DDR_odt,
    inout               DDR_ras_n,
    inout               DDR_reset_n,
    inout               DDR_we_n,
    inout               FIXED_IO_ddr_vrn,
    inout               FIXED_IO_ddr_vrp,
    inout   [53:0]      FIXED_IO_mio,
    inout               FIXED_IO_ps_clk,
    inout               FIXED_IO_ps_porb,
    inout               FIXED_IO_ps_srstb,

    input               key,
    output              led
    );

wire                clk_acq;
wire                rst_n;
wire                trigger;
wire    [38:0]      pin_39;
wire    [63:0]      fifo_din;
wire    [31:0]      pl_cnt;

assign led = pin_39[20];

trigger_out  u_trigger_out (
    .clk                     ( clk_acq      ),
    .rst_n                   ( rst_n        ),
    .key                     ( key          ),

    .trigger                 ( trigger      )
);

pin_out  u_pin_out (
    .clk                     ( clk_acq          ),
    .rst_n                   ( rst_n            ),

    .pin                     ( pin_39    [38:0] )
);

acquire  u_acquire (
    .clk                     ( clk_acq                  ),//? slow
    .rst_n                   ( rst_n                    ),//TODO 
    .pin_39                  ( pin_39            [38:0] ),
    .pl_cnt                  ( pl_cnt            [31:0] ),
    .trigger                 ( trigger                  ),
    .acq_done                ( acq_done                 ),

    //? FIFO
    .fifo_full               ( fifo_full                ),
    .fifo_almost_full        ( fifo_almost_full         ),
    .fifo_wr_rst_busy        ( fifo_wr_rst_busy         ),
    .fifo_wr_en              ( fifo_wr_en               ),
    .fifo_din                ( fifo_din          [63:0] )
);

pin2axi  u_pin2axi (
    .fifo_wr_en             ( fifo_wr_en                ),
    .fifo_din               ( fifo_din          [63:0]  ),
    .fifo_full              ( fifo_full                 ),
    .fifo_almost_full       ( fifo_almost_full          ),
    .fifo_wr_rst_busy       ( fifo_wr_rst_busy          ),

    .acq_done               ( acq_done                  ),
    .trigger                ( trigger                   ),
    .pl_cnt                 ( pl_cnt            [31:0]  ),

    .clk_acq                 ( clk_acq                   ),
    .rst_n                   ( rst_n                     ),

    .DDR_addr                ( DDR_addr           [14:0] ),
    .DDR_ba                  ( DDR_ba             [2:0]  ),
    .DDR_cas_n               ( DDR_cas_n                 ),
    .DDR_ck_n                ( DDR_ck_n                  ),
    .DDR_ck_p                ( DDR_ck_p                  ),
    .DDR_cke                 ( DDR_cke                   ),
    .DDR_cs_n                ( DDR_cs_n                  ),
    .DDR_dm                  ( DDR_dm             [3:0]  ),
    .DDR_dq                  ( DDR_dq             [31:0] ),
    .DDR_dqs_n               ( DDR_dqs_n          [3:0]  ),
    .DDR_dqs_p               ( DDR_dqs_p          [3:0]  ),
    .DDR_odt                 ( DDR_odt                   ),
    .DDR_ras_n               ( DDR_ras_n                 ),
    .DDR_reset_n             ( DDR_reset_n               ),
    .DDR_we_n                ( DDR_we_n                  ),
    .FIXED_IO_ddr_vrn        ( FIXED_IO_ddr_vrn          ),
    .FIXED_IO_ddr_vrp        ( FIXED_IO_ddr_vrp          ),
    .FIXED_IO_mio            ( FIXED_IO_mio       [53:0] ),
    .FIXED_IO_ps_clk         ( FIXED_IO_ps_clk           ),
    .FIXED_IO_ps_porb        ( FIXED_IO_ps_porb          ),
    .FIXED_IO_ps_srstb       ( FIXED_IO_ps_srstb         )
);
endmodule
